1. Field of the Invention
The present invention generally relates to a central processor unit (CPU) having a cache memory and a cache control method therefor and, more particularly, to a CPU with a cache memory which is useful in executing a program by fetching it from a memory unit.
2. Description of the Related Art
Generally, in an electronic computer, a memory unit having a larger storage capacity needs a larger-scale logical architecture and, therefore, takes a longer period of time in reading data out of the memory. Hence, although the processing rate of a CPU built in the computer may be increased, the overall processing rate of the computer cannot be increased unless the CPU is capable of calling a program of interest at a higher speed.
In the light of the above, some modern computers have a high-speed buffer memory called a cache memory which is successful in reducing the difference between the processing rate of a CPU and the access time necessary for a desired program to be called from a memory unit or main storage. Specifically, a program is called via the cache memory so that the access time of the main storage may follow the processing rate of the CPU.
The cache memory is a small capacity storage and has two different functions, i.e., the function of reading necessary data out of a large capacity storage or memory unit to transfer it to a processing section included in the CPU, and the function of storing a block of data having a predermined size and including data surrounding the block of data read out of the memory unit together with the data read from the memory unit. More specifically, the cache memory stores data transferred from the memory unit and data surrounding the transferred data. When data to be accessed is present in the data so stored in the cache memory, the CPU directly transfers it to its processing section without accessing the memory unit. It follows that when the CPU hits necesary data successively, the processing rate will be further increased.
However, when a CPU buit in a computer fetches a necessary program from a memory unit to execute it often accesses operands randomly although tending to access instructions sequentially in the order of their addresses. This brings about a problem when it comes to a device of the type reading a program by use of a single cache memory. Namely, writing operands to the single cache memory would disturb the cache processing of instructions being sequentially executed and thereby lower the hitting rate.
In the light of the above, a CPU with two independent cache memories each being exclusively assigned to respective one of instructions and operands has been put to practical use. Typical of this type of CPU is a general-purpose cumputer, FACOM-M780 (tradename) announced by Fujitsu Limited in 1985. See Saburo Kaneda, "General-Purpose Computer", Transactions of the Institute of Electronics, Information and Communication Engineers of Japan, Vol. 73, No. 4, pp. 344-350 (April 1990).
With the CPU having two cache memories as stated above, it has been customary to execute a subroutine or similar program by interrupting or transferring the processing while a certain program as a main program is under way, in the manner described below.
When control is transferred from the main program to a subroutine program, none of the cache memories have been loaded with information associated with the subroutine. The CPU, therefore, accesses the operand cache first so as to transfer the first information of the subroutine program, i.e. a module header stored in a memory unit or main storage to its processing section. In this instance, a block of data including the module header and data surrounding it is written to the operand cache.
By referencing the module header, the CPU calles a subroutine program or similar module program. Specifically, the CPU fetches the first module instruction included in the module program from the main storage to an instruction control thereof via the instruction cache. At this time, a block of module instructions including the first instruction are written to the instruction cache. The instruction control decodes the first module instruction and executes it. Thereafter, the instruction control sequentially reads, and executes successive module instructions which were written to the instruction cache. On the other hand, data to be used along with the instructions are read out of the main storage and transferred to a processing section via the operand cache. In this instance, the operand cache also stores a block of data including data surrounding the data read out. On completion of the module program, the operation returns to the main program.
As state above, the conventional cache control method is such that to call a subroutine or similar module program for executing it, a module header heading the subroutine program stored in the main storage is fetched to the operand cache first so as to register a block of data adjacent to the module header, despite the module header being used only once. This brings about a problem that when the operand cache is used afterwards, the hitting ratio of the cache and, therefore, the utilization efficiency thereof are lowered.
Moreover, when the CPU reads the module header out of the main storage or executes the module instructions of the subroutine program, the instruction cache has not yet been loaded with the module instructions. Hence, the CPU has to read the module instructions out of the main storage, resulting in a substantial access time.